Changes:
0.833
SPC700: Fixed timing of MOVW da,YA opcode, thanks to anomie for research [TRAC]
SPC700: Added a brief delay before code execution begins approximating the time taken by reset [TRAC]
5A22: Added DMA setup delay of two slow bus-cycles [TRAC]
Timing: Mostly corrected H-IRQ and H-counter timing for positions after the ´long´ dots near the end of scanlines [TRAC]
Timing: Adjusted hardware interrupt timing, thanks to some info from DMV27 [TRAC]
Timing: Fixed latch behavior with respect to I/O port; improved latch reporting code [TRAC]
5A22: Moved WAI delay to after hardware interrupt detection, thanks to anomie for verifying this [TRAC]
SPC700: Improved flag behavior of ADDW, SUBW, and MUL opcodes, thanks to anomie for research [TRAC]
SPC700: Fixed some issues in timers [TRAC]
SPC700: Improved timer accuracy and behavior of register area, thanks to research from anomie [TRAC]
Source: Removed support for double-clocked SPC700 execution rate [TRAC]
JMA Support: Fixed some bugs in decompression, improved performance, reduced memory requirements, upgraded stream support, and added support for JMA v1 files [Nach]
Sound: Corrected BRR fetches across end of address space to wrap and continue fetching and to not terminate channel, thanks to anomie for research [TRAC]
Sound: Adjusted some aspects of DSP reset [TRAC]
Sound: Fixed a bug in decoding of BRR blocks with invalid range values; thanks to anomie for pointing this out [TRAC]
Source: Improved some aspects of makefiles and source layout [TRAC]
5A22: Added emulation of the capability of HDMA to be used for reading the B-bus, thanks to anomie for alerting me to its presence [TRAC]
SPC700: Removed ´dirty´ opcode fetching [TRAC]